The invention relates to memory devices that involve the polarization state of a ferroelectric capacitor and is specifically directed to the sensing of the memory state. Since the difference in signal-level between polarization states typically is small in such memories, it is useful to employ a preamplifier to increase the signal levels to values that can easily be handled by conventional sense circuits. While the invention is directed to sensing ferroelectric memory signals, it could be employed in any circuit function that involves responding to the charge transferred by a capacitor. In the memory sensing application, the memory being sensed typically involves a substantial bit-line capacitance.
In a ferroelectric memory array, a selected bit line is coupled to a plurality of ferroelectric-capacitor memory elements, one of which is accessed by a suitable decoder. The selected capacitor is pulsed from a drive line causing a pulse to appear on the bit line. The pulse amplitude is a function of the ferroelectric state of the capacitor dielectric and is determined by the ratio of the memory-capacitor value to the bit-line capacitance. Such a capacitive voltage divider will produce the highest voltage when the memory capacitor is large with respect to the bit line capacitance. However, in order to develop maximum voltage across the memory capacitor, thereby aiding to differentiate between its polarization states, the memory capacitor should be made small with respect to the bit-line capacitance. Thus, a compromise must be made with the typical memory capacitor selected to have a value that approximates the bit-line capacitance. An undesirable constraint thus is imposed on the bit-line length in a large memory array.
In view of the foregoing, it would be desirable to provide a sense amplifier that develops maximum voltage across the ferroelectric capacitor and still provides substantial voltage change at its output. Moreover, if voltage change across the bit-line capacitance can be restricted to a small value, performance can be made insensitive to the size of the bit-line capacitance and thus to bit-line length.